Multi-Product Shuttle (MPS) EDA Software Engineer

Job Details:

Job Description:

Intel's Multi-Product Shuttle (MPS) Software Engineering team within the Foundry Technology Development Engineering group is looking for an EDA tools Software Design Automation Engineers.

These engineers will support various aspects of VLSI design automation tasks includes but not be limited to:

• Defining and implementing verification scripts/flows to ensure TestChip designs meet tapeout requirements.
• Developing computer aided design (CAD) automation flows for physical design verification, Design Rule Checking (DRC), layout synthesis and validation.
• Performing audits of VLSI layout to help ensure layout convergence for tapeout schedule readiness and design database acceptance for tapeout.
• Providing customer support to TestChip passengers during design tapeout executions (includes design rules, fullchip layout collaterals, tapeout requirements/procedure).

Successful candidates should exhibit the following behavioral traits:

• Communication skills with the ability to convey technical contents.
• Attention to details and tolerance to ambiguity.
• Highly motivated individual with a 'can-do' attitude, willingness to take informed risks in order to achieve desired team goals.
• Strong communication skills with the ability to clearly/concisely convey technical content, teamwork, and ability to meet the deliverables schedules.
• Attention to details and discipline in implementing defined methodologies.
• High tolerance to ambiguity, ability to efficiently define concrete architecture and design strategy/plans.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience.

Minimum Qualifications:

- Bachelor's or Master's degree in Electrical Engineering or Computer Engineering and/or similar engineering degree.

- 5+ years of experience in at least three of the following:

• Experience in VLSI circuit, CMOS layout design and validation.
• Exposure with industry standard integrated circuits (IC) design CAD tools/flows. Specific experience with CAD tools like Siemens Calibre, Cadence Virtuoso or Synopsys IC WorkBench is required.
• Experience with software development/programming in high-level languages (e.g. Perl/Python/ Shell/TCL/C++) and IC CAD tool scripting languages (e.g. Siemens Calibre or Synopsys ICValidator).
• Demonstrated capacity to solve complex problems using efficient computer algorithm and effective programming techniques.
• Demonstrated expert level understanding of layout design rules and familiar with runset or rule-deck coding development.

Preferred Qualifications

-- Experience working on with UNIX/Linux computer platforms.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$144,501.00-$217,311.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.